The invention relates to semiconductor processing, and more particularly to an improved method for forming a buried plate such as used in a trench capacitor of an advanced microelectronic device, e.g., a dynamic random access memory (DRAM).
A goal of the semiconductor industry is to increase the circuit density of integrated circuits (“ICs” or “chips”), most often by decreasing the size of individual devices and circuit elements of a chip. Trench capacitors are used in some types of DRAMs for storing data bits. Often, increasing the circuit density of such DRAMs requires reducing the size of the trench capacitor, which, in turn, requires reducing the area of the chip occupied by the trench capacitor. Achieving such reduction in surface area is not straightforward, because different components of the storage capacitor do not scale at the same rate, and some components cannot be scaled below a certain size. It would be desirable to provide a process of forming a trench capacitor which helps maintain the lateral dimensions of the trench capacitor within the tolerances at the surface of the chip required to achieve further reductions.
The fabrication of a trench capacitor begins by etching an opening in a semiconductor substrate. A trench capacitor is typically formed by a series of process steps, starting by etching a deep trench in a semiconductor region of a substrate. A patterned pad stack is generally provided on the substrate to define a window through which the opening is to be etched.
The trench capacitor is a plate capacitor, having as a first plate a “buried plate”, which is a charge-containing region in the semiconductor substrate adjacent to the sidewall of the trench. A second plate of the capacitor is provided as a “node electrode”, separated from the buried plate by a thin “node dielectric.” The buried plate is typically disposed adjacent to only a lower portion of the trench, while an isolation collar is provided in the upper portion of the trench to isolate the trench capacitor from other nearby devices such as transistors. The buried plate is typically formed by outdiffusion of dopants from a dopant source into the lower portion. Typically, the dopant source is one that provides dopants, such as arsenic-doped silicate oxide, i.e., arsenic-doped glass (ASG). The dopant source is deposited to cover the sidewalls and bottom of the trench, such as through a low-pressure chemical vapor deposition (LPCVD) process. Thereafter, an annealing process is conducted to drive the dopants into the adjacent areas of the substrate to form the buried plate.
Unfortunately, conventional processing using ASG as a dopant source is not ideal. The ASG deposition tends to oxidize the semiconductor material at the sidewall of the deep trench. The ASG deposition also tends to cause dopant diffusion into the semiconductor material beyond the oxidized layer that forms at the semiconductor surface. These problems are illustrated with reference to FIG. 1.
FIG. 1 is a cross-sectional view illustrating a stage in the formation of a buried plate for a trench capacitor according to a prior art process. As shown in FIG. 1, a trench 105 is vertically etched into the semiconductor substrate 100 through an opening 115 in a pad stack 130. The sidewall 110 of the trench represents the edge of the semiconductor substrate, as stands after first etching the trench 105, before subsequent processes are performed. Illustratively, a layer 112 of ASG is deposited onto the sidewall 110 and bottom 145 of the trench 105 as a source of dopant material for later forming the buried plate. However, as a result of the deposition of the ASG, an oxide layer 150 forms due to the oxidation of the semiconductor substrate adjacent to the original trench sidewall 110. The oxide region 150 extends outwardly from the original trench sidewall 110 to a post-oxidation sidewall 140, thus widening the lateral dimension of the trench to the sidewall 140. The widening of the upper portion 180 of the trench is undesirable, because it negatively impacts the overlay tolerance. In addition, arsenic outdiffuses into the region 190 of the substrate adjacent to the oxidized region 150 during the ASG deposition process. Doping the upper trench portion 180 is undesirable because it increases the device leakage current and negatively impacts device performance.
FIG. 2 illustrates a subsequent stage in the conventional process of forming a buried plate, after a dopant drive-in anneal has been conducted. As shown, a buried plate 102 is disposed in the substrate surrounding a lower portion 170 of the sidewall of the trench 105. Illustratively, a layer 200 of an undoped oxide is disposed as a cap to protect the upper portion 180 of the trench sidewall from unwanted doping during the anneal process to drive dopants diffusing into the lower portion 170 of the trench. The cap layer 200 is formed after the undesired oxide 150 (FIG. 1) and the ASG layer have been removed from the upper portion 180 of the post-oxidation sidewall 140 of the widened trench.
FIG. 3 illustrates a further stage in fabrication, after a buried plate 102 has been formed. The trench with widened upper portion 180 is further illustrated in FIG. 3 as an increase in a lateral dimension 310, as measured by the spacing bounded by the post-oxidation trench sidewall 140. This increased dimension 310 is shown in relation to the original lateral dimension 305 of the trench, as represented by the original location 210 of the trench sidewall 110 (FIG. 1).
The two problems of trench widening and diffusion of arsenic into the substrate adjacent to the upper portion of the trench negatively impact the performance of the trench capacitor and the ability to maintain process tolerances. Both problems are due to the direct deposition of dopant source material (e.g., ASG) on the sidewall of the semiconductor substrate. Accordingly, a new method is desired to address the foregoing concerns.